AI, or better yet machine learning, has unique requirements that are being used on how systems are built and deployed. The AI architectural revolution is being utilized by major software companies. This includes Google, Apple, IBM, Intel, Facebook, and others. The companies are utilizing neural processors that will essentially accelerate the neural networks. They deploy co-processors that run AI models, however, with the demand for intelligent applications evolving, systems will need to do more to adapt.
The reason for this process is based on AI systems having a unique I/O requirements. Neural processors don’t have caches and don’t need floating point numbers, and their I/O overhead.
In today’s era of computers, it’s common for applications to use many frames at a high resolution. As a result, it stresses the I/O subsystem. This is a usual occurrence in neural networks that stream data.
Computer scientist and architects are still learning the logistics on how to optimize data structures and data representation for an enhanced performance. However, it’s been clear data x86 architectures will not be the preferred method of AI platforms.
Memory access plays a critical role when factoring in AI. For example, a scalable interconnect may port DNN accelerators and wide DRAM controller interfaces. In today’s Deep Neural Network (DNN) it’ll assume the availability of the read and write ports. Typically ports being 8 or 16 bits with independent DRAM access. A memory interconnect uses a complex wide DRAM controller to interface the number of narrow read and write ports.
Unlike many memory busses, the DNN is efficiently used when DRAM bandwidth is portioned evenly across the DRAM ports. DRAM can consume the energy of up to 90%, which minimizes memory logic. Using it more efficiently can be critical because it’ll have a major impact cost savings for mobile devices and warehouse-scale computers.